In a method of manufacturing an electronic device using a semiconductor wafer (hereinafter simply referred to as a “wafer”), for example, a film forming step of forming a conductive film or an insulating film on a surface of the wafer, a lithography step of forming a photoresist layer of a prescribed pattern on the conductive film or the insulating film thus formed, an etching step of forming the conductive film into a gate electrode by plasma generated from a processing gas or forming a wiring hole or a contact hole in the insulating film, using the photoresist layer as a mask, or the like are executed.
For example, in a certain method of manufacturing an electronic device, a groove is formed in a predetermined pattern on a polysilicon film 80 formed on the surface of a wafer W, and subsequently, a SiO2 layer 81 which is an oxide film for filling the groove is formed (FIG. 7A). Then, the SiO2 layer 81 thus formed is partially removed by etching or the like so as to have a predetermined thickness.
At this time, as a method of removing the SiO2 layer 81, a substrate treatment method is known in which a wafer W is subjected to a COR (Chemical Oxide Removal) process and a PHT (Post Heat Treatment) process. The COR process is a process of chemically reacting the SiO2 layer 81 with gas molecules to generate a reaction product. The PHT process is a process of heating the wafer W subjected to the COR process and removing the reaction product produced in the COR process from the wafer W by sublimation.
As a substrate treatment apparatus for executing the substrate treatment method which performs the COR process and the PHT process, a substrate treatment apparatus has been used that includes a chemical reaction processing chamber (COR process chamber) and a thermal processing chamber (PHT process chamber) connected to the chemical reaction processing chamber (see, for example, Patent Document 1). In addition, a substrate treatment apparatus has been used that performs, in a common processing chamber, a COR process on the wafer W at a low temperature and subsequently, performs a PHT process by heating a wafer W to a predetermined temperature (see, for example, Patent Document 2). In any of the substrate treatment apparatuses, a hydrogen fluoride (HF) gas and an ammonia (NH3) gas are used in the COR process, and a reaction product is produced from the SiO2 layer 81.